The present invention relates to semiconductor memory devices, and, in particular relates to NAND flash memory devices.
Semiconductor memory devices are storage units that may be capable of storing data and providing data in response to requests therefor. These semiconductor memory devices are generally divided into random-access memories (RAMs) and read-only memories (ROMs). RAMs may be volatile memories that lose data when a power supply is absent, while ROMs may be nonvolatile memories that keep data even without a power supply. RAMs may include dynamic and static types. ROMs are usually classified into programmable ROMs (PROMs), erasable PROMs (EPROMs), electrically EPROMs, and flash memories. The flash memories may be divided into NOR and NAND types.
FIG. 1 is a circuit diagram showing the structure of a cell string in a conventional NAND flash memory device. As illustrated in FIG. 1, a cell string is composed of a ground selection transistor GST, a string selection transistor SST, and pluralities of memory cells MC0˜MC31 serially connected between the ground and string selection transistors GST and SST. The ground selection transistor GST is connected to a common source line CSL while the string selection transistor SST is connected to a bitline BL.
Wordlines WL0˜WL31 are each coupled to gates of the memory cells MC0˜MC31 so as to apply wordline voltages thereto. The gate of the string selection transistor SST is coupled to a string selection line SSL while the gate of the ground selection transistor GST is coupled to a ground selection line GSL.
A voltage of 0V is applied to a bitline PGM_BL that is connected to a memory cell to be programmed (hereinafter, referred to as “program cell”), while a power source voltage Vcc is applied to a bitline IHB_BL that is connected to a memory cell not to be programmed (hereinafter, referred to as “program-inhibited cell”).
Assuming an intention to program the memory cells MC0′ and MC0, which are coupled to the wordline WL0 adjacent to the ground selection line GSL, a program voltage Vpgm is applied to the selected wordline WL0 and a pass voltage Vpass is applied to deselected wordlines WL1˜WL31 during a programming operation. During this operation, the program cell MC0′ has a threshold voltage corresponding to data ‘0’ and the program-inhibited cell MC0 has a threshold voltage 1corresponding to data ‘1’ as an erased state.
FIG. 2 is a timing diagram showing bias conditions for a programming operation for the cell string of the NAND flash memory device shown in FIG. 1, which depicts variations of channel voltages in the program cell MC0′ and the program-inhibited cell MC0 during the programming operation.
When the programming operation begins, the bitline PGM_BL of the program cell MC0′ is set to 0V while the bitline IHB_BL of the program-inhibited cell MC0 is set to the power supply voltage Vcc.
The power source voltage Vcc is applied to the string selection line SSL at time point t1. At this time, a channel voltage of the program-inhibited cell MC0 is Vcc−Vth. Here, Vth represents a threshold voltage of the string selection transistor SST. As a result, the string selection transistor SST cuts off.
At time point t2, the voltage being applied to the string selection line SSL transitions to a voltage Vsel that is greater than the threshold voltage Vth but less than the power source voltage Vcc, which forces the string selection transistor SST to be driven heavily into a cut-off state.
At time point t3, a high voltage of about 8V, which is the pass voltage Vpass, is applied to the selected wordline WL0 and the deselected wordlines WL1˜WL31. If the pass voltage Vpass is applied to the gate of the program-inhibited cell MC0 through the selected wordline WL0, capacitance-coupling between the channel and gate of the program-inhibited cell MC0 may be generated. The capacitance-coupling may boost the channel voltage, which is called a self-boosting effect. The boosted channel voltage may prevent the F-N tunneling effect from being induced in the program-inhibited cell MC0.
However, as shown in FIG. 2, when the pass voltage Vpass is being applied to the wordlines WL0˜WL31, voltages on the ground and string selection lines GSL and SSL instantly rise because there is a line capacitance-coupling effect between the selected wordline WL0 and the ground selection line GSL or between the wordline WL31 and the string selection line SSL.
The voltages on the ground and string selection lines GSL and SSL instantly rise due to the line capacitance-coupling effect. If the voltages on the ground and string selection lines GSL and SSL are slightly raised, then the ground selection transistor GST or the string selection transistor SST is instantly turned on, thereby failing to maintain its cut-off state. During this operation, the channel voltage Vboost of the program-inhibited cell MC0, which has been raised by the self-boosting effect, leaks out through the ground selection transistor GST or the string selection transistor SST. Thus, as shown in FIG. 2, the channel voltage Vboost of the program-inhibited cell MC0 becomes lower.
At time point t4, when the program voltage Vpgm is applied to the selected wordline WL0, electrons staying at the channel are injected into the floating gate in the program cell MC0′. But, in the program-inhibited cell MC0′, electrons should not be injected into the floating gate from the channel because there is no generation of the F-N tunneling effect.
However, as shown in FIG. 2, the decreased channel voltage of the program-inhibited cell MC0 may induce the F-N tunneling effect therein. Namely, the program-inhibited cell MC0 is inadvertently programmed thereby. Such a result causes degradation of a distribution profile for programmed threshold voltages of memory cells. The distribution profile for programmed threshold voltages may be highly important for multi-level memory cells each storing multiple data bits. Thus, the channel-voltage leakage due to the capacitance-coupling effect between the wordline and selection lines may become more serious in programming multiple data bits.